FPGA 10/13 · Saleae Claude — Measurement as Proof

The problem

Relying on simulation or internal debug cores creates a feedback loop where systematic errors remain hidden. Without independent external measurement, performance claims are self-reported predictions rather than verified hardware reality.

What it does

• Plans hardware captures by calculating required sample rate margins and trigger points against simulation predictions.
• Configures protocol decoders for UART, SPI, and I2C based on actual driver implementation rather than generic datasheets.
• Executes bit-for-bit comparisons between physical signal captures and RTL simulation traces to identify regressions.
• Calculates separate timing metrics for raw kernel execution versus end-to-end system paths to prevent inflated speedup claims.
• Generates cryptographically sealed capture archives with SHA-256 hashes for chain-of-custody verification.

Frameworks & tools

Saleae Logic hardware and software, SPI, I2C, UART protocols, RTL simulation traces, and Python-based sealing scripts.

Why this beats prompting it yourself

Generic prompts often miss subtle protocol misconfigurations like SPI clock phase mismatches or insufficient oversampling. This skill enforces a strict measurement-before-prediction workflow and automates the custody hashing required for rigorous hardware audits.

Use cases

• Verifying FPGA accelerator throughput against simulated benchmarks.
• Debugging communication mismatches between driver software and RTL implementations.
• Auditing hardware performance for official technical reports and client delivery.
• Disclosing logic overhead caused by internal embedded logic analyzers.

Known limitations

Requires physical Saleae logic analyzer hardware and broken-out signal pins or headers for external measurement.