FPGA 04 Verilog Claude

The problem

Writing Verilog that passes simulation but fails on hardware is a common frustration. Unintended latches, blocked carry chains, and clock-domain crossing errors often stay hidden until synthesis or board deployment.

What it does

• Generates synthesizable RTL optimized for FPGA structures like LUTs, fast-carry chains, and block RAM.
• Enforces strict blocking vs. nonblocking assignment discipline to prevent simulation-synthesis mismatches.
• Implements canonical three-process FSMs with safe recovery paths and one-hot encoding options.
• Handles clock-domain crossings using two-FF synchronizers, Gray code, or handshake protocols.
• Eliminates unwanted latches by ensuring complete case/if-else coverage in combinational blocks.

Frameworks & tools

Works with Verilog-2001 and SystemVerilog (always_comb, always_ff). Optimized for FPGA synthesis tools from vendors like Xilinx (Vivado) and Intel (Quartus).

Why this beats prompting it yourself

Generic LLMs often produce simulation-only code or "spaghetti RTL" that ignores hardware constraints. This skill applies specific architectural knowledge to ensure your logic maps to physical FPGA primitives rather than generic gates.

Use cases

• Translating a verified functional spec into synthesizable RTL modules.
• Debugging "inferred latch" warnings in complex combinational logic.
• Implementing safe asynchronous FIFO pointers and clock-domain interfaces.
• Optimizing arithmetic units for fast-carry chain utilization.

Known limitations

Focuses on RTL generation; file I/O and simulation-only constructs are restricted to testbench code. Requires a clear functional specification to produce bit-accurate hardware.