FPGA 02/13 · Golden Python Claude — The Oracle

The problem

Hardware verification often fails because the reference model is "soft." Without proven error bounds and explicit status flags, every deviation between RTL and Python results in a debugging meeting instead of a mechanical pass or fail.

What it does

• Hardens Python specifications into pure, stateless reference functions (oracles) with zero I/O or timing behavior.
• Calculates and justifies accuracy targets, specifically choosing between faithful rounding (under 1 ulp) and correct rounding (0.5 ulp) based on provability.
• Expresses all tolerance bounds as multiples of Unit in the Last Place (ulp) to ensure scaling across different output formats.
• Generates complete truth tables for small input spaces to ensure 100% test coverage rather than randomized sampling.
• Produces explicit status flags for edge cases and out-of-range inputs instead of hiding errors in return values.

Frameworks & tools

Python, FPGA/ASIC verification workflows, and hardware description languages like Verilog or VHDL.

Why this beats prompting it yourself

Standard LLM prompts often produce "correct-looking" math that breaks during RTL integration. This skill enforces strict error chain analysis and ulp-based tolerances, preventing the "Table Maker's Dilemma" and ensuring your reference model is a provable mathematical oracle.

Use cases

• Creating a golden reference model for fixed-point DSP hardware blocks.
• Generating 100% coverage truth tables for 6-bit or 8-bit lookup table (LUT) logic.
• Proving error bounds for complex transcendental functions using virtual intermediate values.
• Establishing seed discipline and repetition counts for randomized hardware stress tests.

Known limitations

Does not handle I/O, file access, or interface logic. The oracle is strictly a pure mathematical function.